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315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Pin Description
TSSOP
1
PIN
THIN QFN
29
NAME
XTAL1
FUNCTION
Crystal Input 1 (See the Phase-Locked Loop section)
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V
low-dropout regulator, and should be bypassed to AGND with a 0.1μF capacitor as close as
2, 7
4, 30
AVDD
possible to the pin. Pin 7 must be externally connected to the supply from pin 2, and bypassed
to AGND with a 0.01μF capacitor as close as possible to the pin. (See the Voltage Regulator
section and the Typical Application Circuit .)
3
4
5, 10
6
8
9
31
32
2, 7
3
5
6
LNAIN
LNASRC
AGND
LNAOUT
MIXIN1
MIXIN2
Low-Noise Amplifier Input (See the Low-Noise Amplifier section)
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground
to set the LNA input impedance (See the Low-Noise Amplifier section).
Analog Ground
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter (See the Low-
Noise Amplifier section).
1st Differential Mixer Input. Connect to LC tank filter from LNAOUT.
2nd Differential Mixer Input. Connect through a 100pF capacitor to V DD3 side of the LC tank.
Image-Rejection Select. Set V IRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
11
8
IRSEL
unconnected to center image rejection at 375MHz. Set V IRSEL = V DD5 to center image
rejection at 433MHz.
12
13
14
15
16
17
18
19
20
21
22
23
9
10
11
12
14
15
16
17
18
19
20
22
MIXOUT
DGND
DVDD
AC
XTALSEL
IFIN1
IFIN2
DFO
DSN
OPP
DFFB
DSP
330 Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
Digital Ground
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a
0.01μF capacitor as close as possible to the pin. (See the Typical Application Circuit .)
Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100k Ω resistor.
Crystal Divider Ratio Select. Drive XTALSEL low to select f LO /f XTAL ratio of 64, or drive
XTALSEL high to select f LO /f XTAL ratio of 32.
1st Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF
capacitor as close to the pin as possible.
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a
10.7MHz bandpass filter.
Data Filter Output
Negative Data Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Positive Data Slicer Input
+5V Supply Voltage. Bypass to AGND with a 0.01μF capacitor as close as possible to the pin.
24
23
V DD5
For +5V operation, V DD5 is the input to an on-chip voltage regulator whose +3.2V output
appears at the pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application
Circuit .)
25
24
DATAOUT Digital Baseband Data Output
26
27
26
27
PDOUT
SHDN
Peak-Detector Output
Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with
a 100k Ω resistor.
8
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